An economical determinant of integrated circuit process technology is the yield, that is the percentage of the total number of chips processed that are good. Often, bad chips are caused by devices wherein they fail to operate because of excessive leakage currents. The yield of complex integrated circuits is typically a few percent. One major factor that affects this yield is the presence of crystal defects in silicon, or other semiconductor wafers on which integrated circuits are built. These crystal defects can be classified into two kinds: the native defects, such as dislocations, stacking faults, and clusters of self-interstitials and vacancies; and the extraneous defects, such as contaminants of elements different from the semiconductor substrates. Dislocations are introduced in high temperature processing because of non-ideal thermal conditions (see for example, K. Morezane and P. S. Gleim, J. Appl. Phys. 40, 4104 (1969); S. M. Hu, App., Phys. Lett. 22, 261 (1973)), whereas stacking faults are introduced either during epitaxial growth when the substrates are not appropriately cleaned (see, for a review, B. A. Joyce, Rept. Prog. Phys. 37, 363-420 (1974), or during thermal oxidation when the substrates contain other kinds of point defect clusters serving as nucleation sites (see, for example, D. J. D. Thomas, Phys. Stat. Solidi 3, 2261 (1963); S. M. Hu, Appl. Phys. Lett. 27, 1965 (1976). Clean native defects, in general, are not harmful electrically by themselves to any practical extent. However, they interact with extraneous impurities and become harmful. One example is the formation of transistor "pipes", commonly though as formed by enhanced diffusion of emitter or subcollector dopants along dislocations traversing transistor bases (for example, see F. Barson, M. S. Hess and M. M. Roy, J. Electrochem. Soc. 116, 304 (1969); G. H. Plantinga, IEEE Trans. Electron Devices ED-16, 394 (1969)). Another example is the role of vacancy/interstitial clusters, stacking faults, and dislocations serving as nucleation centers for the precipitation of fast diffusing impurities such as copper (for example, see S. M. Hu and M. R. Poponiak, J. Appl. Phys. 43, 2067 (1972); Phys. Stat. Solidi (a) 18, KS, (1973)), and other fast diffusing impurities such as iron, nickel, gold, etc.
As early as 1960, it was recognized that precipitates of such fast diffusing impurities as copper, iron, nickel, etc. may act to facilitate the recombination/generation of electron-hold pairs, leading to excessively high reverse leakage currents. With this recognition, Goetzberger and Shockley (J. Appl. Phys. 31, 1831 (1960)) first suggested the use of boron or phosphorus doped silicate glass layers to getter these detrimental impurities (see also, S. W. Ing., Jr., et al. J. Electrochem. Soc. 110, 553 (1963)).
As the integrated circuit processing becomes more complex and lengthy, the changes of contamination, during each of the processing steps, become greater and greater. To rely on the high purity of the starting wafers and the meticuluous cleanliness is no longer without risk. Therefore, other gettering processes have been proposed. These include the diffusion of phosphorus or boron into the silicon wafers, for examples, see M. R. Poponiak, W. A. Keenan, and R. O. Schwenker, in Semiconductor Silicon/1973, H. R. Huff and R. R. Burgess, editors, p. 701, Electrochemical Society Softbound Symposium Series, Princeton, N.J.; R. L. Meek, T. E. Seidel and A. G. Cullis, J. Electrochem. Soc. 122, 786 (1975); J. L. Lambert and M. Reese, Solid-State Electron. 11, 1055 (1968); mechanical damages on the wafer backsides, for examples, see E. J. Metz, J. Electrochem. Soc. 112, 420 (1965) and J. E. Lawrence U.S. Pat. No. 3,905,162, Sept. 16, 1975; ion implantation, for example, see T. M. Buck, K. A. Pickar, J. M. Poate and C. M. Hsieh, Appl. Phys. Lett. 20, 485 (1972); Appl. Phys. Lett 22, 238 (1973) and "Impact Sound Stressing for Semiconductor Devices", U.S. Pat. No. 4,018,626 issued Apr. 10, 1977, to G. Schwuttke et al. All these methods involve, in one form or another, certain disorders worked into the substrates.
Such disorders, mechanical damages in particular, can often propagate through the silicon wafers into the active device areas unless later thermal processes are carried out under extremely idealized conditions that are often not met.
Such damages are also difficult to quantify and control. In the case of ion implantation damages, the damaged layers are often too shallow, and may be easily removed during such later processing as oxidation and etching. Furthermore, improper thermal processing may often anneal out such implantation damages, making later thermal processing procedure not easily optimized or compatible.
U.S. Pat. No. 4,018,626 to Schwuttke, et al, and U.S. Pat. No. 4,069,068 to Beyer, et al, suggest the use of a laser for gettering purposes. Pearce, et al, U.S. Pat. No. 4,131,487 is directed to a method for use of a laser with a high energy beam with sufficient power to vaporize the semiconductor material and produce lattice damage and strain in the semiconductor wafer. Each of these patents require that lattice damage is produced to act as gettering sites.